Synchronous dynamic random access memory (SDRAM) devices operate by accessing memory cells in synchronization with a clock signal. The access speed of the device is dependant upon an address decoding time, data sensing timing, and data output driving time. An increase in the clock frequency will increase the access speed requirements. A problem is experienced when the clock frequency exceeds the process speed of internal memory cell access operations. For example, to access a column of a memory array, an address signal is decoded and column select circuitry is activated. The clock speed either needs to be decreased or a more efficient use of the time between clock cycles is needed.
A problem with SDRAM is the volatile nature of the memory cells. Non-volatile memory devices such as flash memory are available, but do not operate in a synchronous manner. One problem with operating a non-volatile memory in a synchronous manner, such as an SDRAM, is the ability to efficiently use available clock cycle times to perform address decode and memory array access operations.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an efficient address decoding system for a memory device. Further, there is a need in the art for a non-volatile memory that has a more efficient address decoding system.